1. Field of the Invention
The present invention relates to a pattern inspection apparatus, a method for performing pattern inspection, and a recording medium. In particular, the present invention relates to a pattern inspection apparatus for inspecting fine patterns, for example, such as semiconductors (LSI), liquid crystal panels, and masks (reticles) for those, all of which are formed according to design data, to a method for performing the pattern inspection therefor, and to a recording medium therefor.
2. Description of the Related Art
For the pattern inspection of wafers in the manufacturing process of semiconductor integrated circuits or the pattern inspection of masks for pattern formation thereof, an optical pattern inspection apparatus with the use of a method called die-to-die comparison is used. This inspection method is a method whereby a defect is found by comparing an image obtained from a die to-be-inspected (die that is an object of inspection) and an image obtained from the equivalent position of a die adjacent thereto.
On the other hand, for the inspection of a mask called a reticle where no adjacent dies exist, a method called die-to-database comparison is adopted. That is, there is used a method where CAD data is converted into an image format and used instead of the adjacent dies and the same inspection as described above is performed. The technology concerned is disclosed, for example, in the U.S. Pat. No. 5,563,702, “Automated photomask inspection apparatus and method.” However, in this technique, since a rounded part of a corner of an actual pattern formed on the wafer is likely to be recognized as a defect. This problem is circumvented by a method of conducting pretreatment to give a rounding to the image obtained from CAD data as a countermeasure. In such a circumstance where the corners are rounded, when the die to database comparative inspection is performed, it is likely that pattern deformation having no necessity of being judged as a defective corner is recognized as a defect, and this may happen frequently even with the above-described pretreatment. Conversely, if a setting that ignores the pattern deformation of the corner is adopted, there arises a dilemma that a minute defect existing somewhere other than in the corners cannot be recognized.
Presently, for masks, inspection on the basis of the die-to-database comparison system has been put into practical use because the mask should be exactly in conformity to the CAD data. However, the pattern transferred on the wafer are allowed to have pattern deformation of such an amount that electrical characteristic and the like are secured, and in practice, the pattern deformation occurs by some extent because of difference of an exposure condition etc.
Moreover, the pattern inspection on the basis of the aforesaid die-to-die comparison system cannot detect the defects that occur all over the dies on the wafer in common caused by the mask failure called the systematic failure. That is, the same defects occur in the die to-be-inspected and in the adjacent dies that are to be compared with the die to-be-inspected, and hence the comparison between the both dies cannot lead to the detection of the defect of an individual die.
To solve the problem, although it has not been put into practical use because of calculation cost, etc., there is proposed matching inspection between the CAD data and the wafer image. Regarding this technique, there is, for example, a literature: “Automatic failure part tracing method for a logic LSI using an electron beam tester,” NEC Technical Report, vol. 50, No. 6, 1997. In this literature, there are disclosed: a method with the use of a projection of wiring edges on the x- and y-axes; a method where wiring corners are focused on; and a method where a genetic algorithm is applied. Moreover, as a method adopted in this literature, there is described a matching method where, after edges have undergone the linear approximation, closed areas are extracted, and those closed areas are used for the inspection. However, neither of those methods can attain an inspection speed that is usable in high-speed inspection and furthermore none of them can perform the matching while detecting the deformation quantity of the pattern.
In addition, presently, there is used the auto defect classification (ADC) that performs the comparison between an image having a defect (defect image) and an image of the adjacent die corresponding to this (reference image). However, unevenness of the luminance of the reference image and the like may affect recognition accuracy. Moreover, there is a case where it is difficult to determine the inside and the outside of the pattern only from the image. In such cases, it is often the case that it is difficult to distinguish between short circuit and deficiency and the like. In addition, since this method cannot give information concerning which pattern is destroyed by the defect, fatal defects to the pattern and a mere defect other than such defects cannot be classified.
The inspection method using the die-to-die comparison intrinsically bears the error arising from staging precision of the inspection apparatus and precision of the optical system, and the error is approximately ten times larger than the wiring pattern width or more. Due to this fact, even when a defect position is projected onto a pattern that the operator wishes to create (design pattern), it is impossible to specify the defect position of the pattern accurately.
Recently, the pattern width of integrated circuits becomes comparable to wavelengths of the light sources to be used in the exposure process, or goes down below the wavelengths. In such pattern formation, a method of adding optical proximity correction (OPC) patterns is adopted. This method is a technique whereby a mask is formed so that the OPC patterns are added to the design data, the exposure is performed using this modified mask, and the manufactured actual pattern on the wafer is made to come close to the design data.
It is impossible for the conventional die-to-die comparison method to inspect whether or not the OPC patterns effectively serve as corrective modification for the pattern on the wafer. Therefore, a solution is required for this problem, for example, a method whereby the comparative examination between the pattern on the wafer and the design data can be performed considering an allowable pattern deformation quantity.
In addition, in a job shop type production (multi-product small-volume production) as is seen, for example, in a system on chip (SOC), a short delivery date is required. In such a case, even if the systematic defect is found at the electric inspection that is the final inspection, a quick countermeasure may not be taken to respond the short delivery time. As a countermeasure of this problem, there has arisen a requirement that the difference between the design data and the formed pattern is monitored in each step of the exposure process. Therefore, an inspection method whereby pattern deformation that doesn't affect the electrical characteristic is set as the allowable pattern deformation quantity and the comparative examination between the design data and the pattern on the wafer can be performed while allowing possible deformations that fall within the allowable pattern deformation quantity.
Moreover, design check is currently in practice using a software program, Lithosimulator, etc., as evaluation of the pattern deformation. In order to verify validity of this simulation, comparative examining devices for comparing between the pattern that litho-simulator outputs (simulation pattern) and the actual pattern are required.
It becomes still more important to improve the technology for circuit design by obtaining the pattern deformation quantity to the design data.
By the way, at present, a CD-SEM (Critical Dimension Scanning Electron Microscope) is used for controlling the pattern width of the wafer in the manufacturing process of semiconductor integrated circuits. This CD-SEM carries out automatic measurement of the line width of a line pattern at a specified position using a line profile for each transfer unit of the stepper called a shot. This measurement is performed for several positions for several shots on several pieces of the wafers for one lot, and whether or not a transfer function of the stepper is normal can be controlled in units of nm (nano meters).
As control items of the circuit pattern, shrink in an endpoint of the wiring, a position of an isolated pattern and the like are also important besides the line width, but the automatic measuring function of the CD-SEM accommodates only one dimensional measurement, that is, the CD-SEM can measure only the length such as the line width. Consequently, the measurement of those two-dimensional shapes is conducted by the operator's visual inspection of the images obtained by the CD-SEM or other microscopes.
Generally, the optical proximity effect correction (OPC) plays an important roll not only to secure the line width of the line pattern but also to form shapes of the corners and isolated patterns. Furthermore, because of improvement of an operating frequency, presently the control of the shape of a top end or base of the gate wiring pattern, called an end cap or a field extension, respectively, also becomes important in addition to the gate line width.
Such shape measurement of two-dimensional patterns as these is essential both in the sampling inspection in the manufacturing process and in a trial production phase, and especially in the trial production phase, it is thought to be requisite to inspect the pattern formation on the whole wafer.
However the present situation is, as described above, that the control of the two-dimensional shape is done by a human work and hence automatization is needed from the point of view of accuracy and productivity.